Qmax QT2256- 320 PXI Software Platform
Qmax TestDirector II (TD2) software consists of TestDirectorII (TD2) Interactive for instant test of a PCB using Qmax's General Purpose Test Adopter, TD2
TestSequencer for sequencing various tests for a board functional test, TD2 TestStation for operator Level use of the Test Program and optional
TD2 TPS Development Studio for generating new Test Program Set.
TD2 Interactive
These tests can be performed on any PCB instantly using clips / probes along Qmax Device Library and or Learn and Compare technique
 | Out-Circuit Test of Devices |
| In-Circuit Test of Devices |
| Open / Short Test |
| RLC Measurements |
| Voltage / Frequency measurements |
| QSM VI Tests |
| Oscilloscope and Function Generator |
| Boundary Scan Tests |
TD2 TestSequencer:
This software package Sequences Test Flow and Guides the user through the entire Test procedure and generates detailed error logs
A typical Test Sequence for a board may contain the following tests
| Open / short test / fixture wiring tests |
| Measurement of RLC, and Diode values |
| QSM VI Tests |
| Board Power supply measurements, Frequency measurements |
| Functional Test using Internal or external resources through edge connector / test points |
| Integrated Boundary Scan Test for BS devices such as ID code read, User code read and Interconnect test. |
| Testing of Non BS devices and logic devices through JTAG pins of BS devices, edge connector and test points. |
| Bus Cycle Signature Test for CPU based boards. |
| DC Parametric Test - Input Bias Current / Output Load test / High Impedance check for Tri-state / Bus Devices |
| External Instrument Test Routines for IEEE or PXI |
TD2 TestStation :
TD2 TestStation is operator level software with password protection along with statistical data / error log and soft operator
console. Test parameters / limits can not be changed here
| Master Board selection from database |
| Enter Board under test details |
| View Board repair history |
| Test Board and log errors |
| Clearly mark failed, suspected components |
| Replace failed / suspected components |
| Test board and repeat process until the board pass. |
| Create Histograms / PIE charts for MIS. |
| Network capability for remote yield monitoring. |
TD2 TPS Development Studio (Optional):
TPS Development studio is used to generate Test Program Set for a PCB under test. Its inputs are Bill of Materials, Net-list and optionally the
Gerber file for PCB layout or Jpeg picture file of the PCB under test using a digital camera. The user can generate digital / analog or mixed
signal test vector for both board initialization and a series of functional test either graphically or using the Qmax’s PythonTD test language –
a high-level open source Test Language. The expected output response of the PCB under test can be Defined using an expression / Mark for learning
from known good board for analog / digital and mixed signals or Simulated using IEEE standard VHDL simulator for digital signals.Features include, Guided Probe Back Tracking,
Fault Tree, PCB layout / PCB Image / Schematic image for paperless repair.
In-Circuit Functional Test:
Qmax’s ICFT / QSM Software Package for In-Circuit test of digital / analog / mixed signal devices including cluster test using 22,000+ Qmax Models.
Test can be carried out using Clips / probes or nail bed.
Device links between pins can be either learnt from a known good board for comparison with a suspect board. OR if netlist is available it can be verified.
Automatic Guarding guide is available while testing Bus devices and the system has the ability to trace links between Bus Devices to determine effective guard pins. Optionally this information can also be extracted from net list if available, while testing Bus Devices and OC / OE devices.
QSM VI Learn / Compare for devices that cannot be modeled and simulated.
Functional Test by Board Level Simulation
For Board Functional Test and Guided Probe Back Tracking diagnostic software, a simulator is used to predict the output response of the Board and its internal nodes and compared with actual output response in detecting faults and to back track the failure. TD2 supports industry standard simulators both off-line and on-line simulation modes. Off-line simulation does not provide any predicted output unless the board under test has been initialized to home state and thus suffers accurate diagnostics in case the board fails to initialize. This is especially significant if the board under test had many state machines / flip-flops and counters and all of them have to be initialized before any simulation can take place. On-line simulation method is pioneered by Qmax over the years and has proven to be accurate in fault diagnosis even if the board under test fails to initialize, since it uses previous states to determine the next state. System allows verification of all the internal nodes with respect to the simulator response and if any mismatch, allows the user to mask unwanted data or to set the test window correctly.
Paper Less WorkStation
While back tracking, the TD2 software can show the schematic view or the Board Layout or the Waveform window or the Back Track Tree for easy probing and diagnosing the fault as thus providing a paper less workstation
Functional Test by Learn and Compare
This method applies, when users cannot generate behavioral description of devices on board either in VHDL. Users enter the Board Net list and generate the input sequence to
initialize the board to a known state. Then for every subsequent test, user can learn the output response of the board through card edge connector and probes for internal nodes.
The learnt outputs are stored in the Master board Database for comparison in faulty boards. Users must ensure the board is initialized before learning output response and that the output
response is repeatable. Net List information is used in guided probe back tracing the origin of fault.
 Functional Test by Combination of Simulation & Learnt method
When devices on board cannot be modeled for behavioral description, it is possible to label them as black boxes and learn their response at their outputs and pass the leant
value in place of simulated value for further simulation of other devices / nodes.
Fault Simulation (Optional)
While using QDDL or VHDL Simulator, Fault Simulator automatically inserts stuck-at-zero (0), stuck-at-one (1) and open (Z) faults in every node in a board and checks that the test program is capable
of detecting them. If the test program covers all the simulated faults, then the confidence is stated as 100%. This helps the ATE Manager to evaluate the test programs before they are put in use.In Learn and Compare technique, insertion of faults and their detection has to be performed manually.
Fault Dictionary(Optional)
Though one can troubleshoot a Board using Functional Test and Guided Probe back tracking, the result depends on accuracy
of the operator in placing the probe on the right nodes. Operator error may lead to incorrect diagnosis. Also in High
density Boards it may be difficult to probe certain nodes and conformal coating may make it more difficult. Alt times
it may not be possible to probe parts of a board when there are daughter boards on top of the main board. Fault
Dictionary provides a mean to improve diagnosis under these circumstances. By the use of Fault Simulation
Software, all possible faults are considered and the resulting output CRC are learnt virtually. By looking
at the CRC code of failure, the system software is able to suggest probable failing components without
having to probe all or if not none. Thus Fault Dictionary greatly minimizes manual probing.
Reverse Engineering
All the available Digital channels (Upto 320) can be used for Reverse engineering (CircuitTracing and Schematic Generation
applications) by using the Qmax Circuit Tracing software and when it is used along with EDWIN software package, the user
can reverse engineer the PCB by creating the schematic diagrams of the PCBs for which there are no circuit diagrams.
User can define any number of Clips / probes and the system will generate the sequence of placing the clips and probes
automatically. The links between devices pins can be learnt and a net list generated. The resistance threshold for a
link can be defined by the user.
|
|
 |
|