Overview
ATE QT2256-320PXI system is designed as a Combination Board Tester capable of testing highly complex and dense PCBs employing various test techniques on a single platform.
It can perform Board Level Functional Test through edge connectors of a PCB, and guided probe diagnostics utility to reliably repair Digital/Analog and Mixed Signal PCBs of various complexities for conventional PCBs.
It is an In-Circuit Device / cluster tester when High Current Pin Driver options are installed and interfaced to the UUT either through clips / probes or nail bed. Standard configuration is 64 Channels high current Pin Drivers.
It has in-built 20MHz 12bit Analog Driver / sensors synchronized with digital drivers for covering analog / mixed signal devices.
Integrated Boundary Scan Test controller (Up to 4 Chains) and software package can be used to test today’s PCBs with high density / high pin count devices. Uses latest technology Boundary Scan hardware with RAM based drivers / sensors in synchronization with ATE digital and analog pin drivers.
To effectively test CPU based boards without excluding the CPU from the test, the system offers optional Qmax patented Bus Cycle Signature System.
In-Circuit Emulator Support for testing DSP based Board Function.
Parametric Measurement Units (PMU) enables testing of the DC parametric of device pins on the edge connector for input bias current, Fan out capacity and Tri-state leakage currents to further enhance fault coverage and avoid unwanted field returns.
Optional AC Parametric Tests for propagation delay, rise / fall time and pulse width measurements.
The capabilities can be further enhanced with optional IEEE instrumentation or PXI based Instrumentation and control through TestDirector II software.
Analog Highways and relay matrix modules are used in routing the test pin to external measurement IEEE or PXI Instruments of user choice.
Uses Virginia Panel Test adapter Interface for highly reliable Unit Under Test (UUT) Interface Panel provides up to 384 signals, 19 power (50A each) and 19 RF connectors.
The ATE is interfaced to an external Host PC using a 32 bit, 33MHz PCI interface card allowing a maximum data transfer rate of 132 Mega bytes per second.
It is a modular design with upgrade options. The basic system comes with 64 High Current Digital Channels, 64 digital channels with 50 Ohms source impedance, 8 Flying channels 2 Analog channels and 5 fixed UUT power supplies. It can be easily upgraded to 320 or more Digital Channels, 4 Analog Channels and with Programmable UUT power supplies, IEEE or PXI External Instrumentation, Bus Cycle Signature System, ICE and Integrated Boundary Scan Test.
State-of-the-art-technology
The heart of the test system is a FPGA based highly programmable dedicated test vector processor with Digital Clock Management System.
It has 4k x 60 bit RAM for Instruction Register and Test Sequencing. Up to 4096 test sequences can be pre-programmed to run automatically with options for
conditional branching. This Test vector processor controls the timing and construction of Drive waveforms that will be driven into the UUT and to acquire
response data. Data formatting capability for NR, RO, RZ, ZD and SBC are supported. All digital channels have 1MB X 8 RAM. All analog channels have 1MB X 24
RAM. The Four Analog Channels can be multiplexed to any of the 320 channels and 8 flying channels. The basic timing unit is programmable from 10 ns to 655us
in steps of 10ns. A Test Cycle with 4 basic timing units results in 40ns data rate or 25MHz test rate. Digital highways provide for synchronization of the
test cycle to UUT events and digital timing measurements through tester pins.
Digital Pin Electronics
There are multiple options for Digital Pin Drivers. These include High
speed 50 Ohms type and High current Back Driving type Pin Drivers. The Drive and threshold levels are programmable. System supports two pallets of Drive and Threshold Level
within +/–10V and in resolutions of 5 mill volts. High Current Back Driving Pin Drivers can select its levels from either of the 2 preprogrammed pallets. The Standard 50 Ohms Pin Drivers
can be individually programmed for it own drive / sense levels. Optionally one can include is a programmable Current Source / Sink up to 35 mA of load current for each Digital Channel to load
output pins and test. The current load can be turned-on or off on the fly.
Programmable Timing Generator / Pin Data Formatter
Basic Timing Unit in QT2256-320PXI is
programmable from 10ns to 655µS. A Test Cycle or Event Frame can be from 4 basic timing units (40ns-min) to 255 timing units. Up to eight Test Cycles can be
pre-programmed. Each of the Test Cycle can have up to eight event pulses preprogrammed. QT2256-320PXI supports NR (Non Return), RZ (Return to Zero), RO
(Return to One), SBC (Surround by compliment) and ZD (Return to Z state) data formats. This feature allows the Drive phase and Test Window to be placed
within a Test cycle using one of the 8 pre-programmed Event Pulses EP0 to EP7.
Analog Sub-System
The Analog Subsystem has maximum of Four Channels with 12 bit
accuracy and 20MHz sampling rate. These four programmable analog channels can be used as stimulus / response channels and are fully synchronized with the
digital channels. They can be used as Analog input / output channels within a voltage range of +/–13V with current capacity of up to +/– 260mA for testing
analog and mixed signal portion of the PCBs under test.
Using two of these analog channels, QSM VI test is carried out for any pin to any pin combination. This QSM VI Learn and compare technique can be used for
these devices, where no data sheet is available, no ICE, no Boundary Scan. This test technique is quite effective in repair.
Enhanced Fault Coverage
They can also be used as DC Parametric Measurement Units (PMUs) that are normally found only in High-end Semi-con test systems. In PMU mode they can Force Voltage and Measure Current (FVMC) or Force Current and Measure Voltage (FCMV). FVMC is used to measure Input Bias Currents of Digital Input pins on the Unit Under Test to compliment the Functional test and ensure the Input Bias Currents are within specification and the Digital Inputs are not over loading their input signals. ATE pin drivers drive up to 50mA or more and thus will be able to drive a faulty input pin that overdraws current and may pass the functional tests. This undetected fault may cause a problem when the PCB is fitted back into the equipment. Conventional ATE does not test this parameter. QT2256-320PXI has higher fault coverage because of this important feature. Similarly, Tri-State output leakage currents can be tested in QT2256-320PXI apart from the functional test. A leaky tri-state pin may cause problem when the board is fitted back in its original equipment. AC parametric measurements help detect timing faults.
Optional AC Parametric Measurements can help measure Set up / Hold times, propagation delay, rise and fall time to ensure reliable operation of the unit under test.
Fully Integrated Boundary Scan (Optional)
This involves testing of Boundary Scan devices using the Test Access Port (TAP) controller (TDI, TDO, TMS, TCK and TRST — Optional), provided in the device. Boundary Scan feature is available in Qmax ATE compliant with IEEE standards 1149.1 for all JTAG formats. All 320 digital channels can also be used in setting up logic levels at the card edge / test pins of the board under test, while executing boundary scan test and thus enabling complete test of the board under test for integrity, functional test for both BS and non BS devices using the Qmax’s exclusive waveform editor including analog for visual test pattern generation and comparison. System support more than one JTAG chain to accommodate BS chains with different voltage levels such as 2.5v, 3.3v or 5v
Signature Analysis (Optional)
In Qmax ATE – QT2256-320PXI, every channel is capable of acquiring logic sates of each digital pin at specified timing strobes. The resultant bit stream is compressed into a 32bit Signature word and thereby building a unique signature for each test channel. Qmax has U.S and U.K Patent rights for their advanced Bus Cycle Signature System to test CPU based boards running on its own clock speed. Each type of CPU will require an external POD to adapt to the test system.
In-Circuit Emulator Option for DSP devices:
There are many popular DSP devices, without Boundary Scan option UUT with In-Circuit Emulator port. The Emulator port is similar to the serial interface. Using the Emulator, one can toggle the Device pins and can carryout functional test of RAM / ROM and other logic devices around the DSP. This may include even ADC / DAC test. Analog voltage forcing and sensing can be done using the Analog channels of the Qmax ATE system.
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