|  | Main test vector processor board with standard timing
generator and Precision timing generator and programmable basic timing unit from 10ns to 655µs |
| | Digital subsystem with 1MB x 4 bits drive RAM, 1MB x 2
bits acquisition RAM and 1MB x 2 bits compare RAM. |
| | Programmable frequency (100KHz to 25 MHz) / mark – space
in the range of 1 to 64 / phase from zero to 127 timing units synchronized / Asynchronous Ram based HF clock output. |
| | Internal 100MHz clock or external clock input (100KHz to
50MHz Max) with phase lock loop and advanced digital clock management. |
| | External event synchronization for up to 64 test pins,
conditional / unconditional loop iterations of up to 32,000 loops. |
| | Digital measurement modes – Leading edge, Trailing edge,
dual edge, window, Glitch and Signature Analysis mode. |
| | Four Digital highways for routing external clock,
frequency measurement, time measurement between two events of UUT pins etc. |
| | Virginia Panel Test adopter Interface for reliable BUT interface provides up to 384 signal pins, 19 power and 19 RF connectors. |
| | Test Jig Adapters for system self test, calibration. |
| | Expandable PXI slots with provision for up to 18 slots. |
| | In-Circuit Measurement unit capable of measuring R / L and C values through analog highways to any test pin or probes or flying channels. |
| | In-built Voltage Resistance Meter and Frequency Counter. |
| | UUT Power Supply: Fixed : +5V@26A max; -5V@26A max
+12V@10A max; -12V@10A max
+3.3V@26A max (650 W Max.);
Programmable :+/-60V@12.5A
max of 5 programmable power supplies can be selected |
| | Optional Foot switch for hands free operation. |
| | TestDirector II TPS Development Studio Software for new TPS development and debug. |
| | Python TD is a high level language similar to Mediator with Menu assisted syntax selection and options. When stepped through, it
shows the generated graphical test patterns in a digital / analog / mixed signal workbench in another window. |
| | Graphical Digital / Analog / mixed signal workbench can also be edited graphically and saved back in Python text. |
| | Simulator can be invoked and expected logic states for output pins viewed in graphical mode. |
| | Probe and Compare / Tailor traces facilities. |
| | Learn mode for non-simulator based test programs. |
| | Integration to Fault Simulation / Fault Insertion Test Program grading applications. |
| | Integration to PCB Layout Gerber files and Digital image of the PCB created by CCD Camera (jpeg files) for probe guiding. |
| | Back Tracking / Forward tracking algorithms and verification utilities. |