In-Circuit Digital Functional Test at its best

1. Functional Test facility for testing individual ICs in In-Circuit or Out of Circuit.
2. Pin Status Check & In-built DRC (Design Rule Checker ).
3. IEEE standard VHDL language in behavioral description of the function of the chip in its library.
4. PythonTD Test language for Analog / Mixed signal device stimulus and output evaluation.
5. Auto compensation is extended for all digital devices ( not limiting to SSI / MSI ) and thus LSI / VLSI chips can be tested in its in-circuit configuration without the need to learn from a known good board.
6. Unified Library of 20K+ devices and device test comprehensives report for validation of Library Test programs developed by a user.
7. Optional VHDL converter for device libraries already written in QDDL ( Qmax Device Description Language ) and WEST ( Waveform Event Specification and Test ).

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User defined QSM VI Stimulus

1. User defined wave pattern as stimulus for VI Trace and thus not limiting the VI trace to simple sine wave alone.
2. User Defined Wave pattern can be any mathematical wave shape such as sine / triangle / square / step / ramp or even arbitrary patterns as desired by user and can be stored in the Library for possible re-use.
3. The frequency is fully programmable from as fast as 1 MHz ( for 10 samples per cycle) down to 1 Hz due to V200's vast time base selection capability.
4. Programmable Amplitude, Source impedance.
5. Use of Step wave is useful in analyzing transient response of node.
6. Incorporates Interactive mode as well as learn and compare.
7. Fixed Reference, any pin to any pin or user combination.

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Measurement functions & other utilities

1. Resistance / Capacitance / Inductance Measurements.
2. Diode Measurements.
3. Frequency Measurements.
4. Period / Time Measurements.
5. 3 Channel - 20 Mega Sample Scope with Programmable Load.

TestSequencer

1. For Sequencing of multiple tests with conditional branching, messaging, user prompting, external trigger and external handshage.
2. Board level Test using combination of ICFT, QSM VI, Measurements, Card Edge Test, Boundary Scan Test, all in one test program.

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TestStation

1. Programs developed in TestDirector II Workstation can be exported to TestStation
2. Test only usage and no program / data / tolerance can be modified.
3. For use by operators in a TestStation.
4. User defined Error Log reporting, Failure analysis, statistics and data log.
5. Network ready for remote monitoring of yield and statistics.

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TDII Basic TPS Developement Studio ( Optional )

Card Edge Functional Test at its best

1. User can develop test program for devices using PythonTD Test Language for generation of test vector and expected output waveform for devices that are digital, mixed signal or analog.
2. Extensive Device / PCB initialization routine support with conditional loops and external event synchronization support.
3. Either defince expected outputs or Learn and Compare with mask / tolerance at user control, when no functional description is available.
4. The Test program developed can be used for a device / cluster or a complete PCB.
5. In case of cluster or whole board, user needs to input the netlist of the circuit, assign input / output pins for tester channel for automatic generation of guided probe back tracking of internal nodes.
6. Sequencing of multiple test programs with conditional branching.

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TDS Advanced TPS Development Studio ( Optional )

1. Includes all the features of Basic TPS Development Studio
2. User can describe the device functionality in VHDL behavioral or structural or even use the device vendor supplied RTL file (Register Transition Logic ) for automatic generation of expected output response.
3. Mentor Graphic's ModelSim PE version Digital VHDL Simulator for predicting expected outputs with advanced On-Line Simulation support for increased fault coverage for boards that fail to initialize.
4. Automatic Guided Probe Back Tracing for Fault Isolation up to node level.
5. Fault Simulation Software for Board Test Program Validation and test comprehensiveness.
6. Fault Dictionary Software for Nil or minimizing internal node probing.
7. Supports external instrumentation through IEEE-488 GPIB / VXI / PXI and signal routing matrix.

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Boundary Scan Test Software ( Optional )

Basic Boundary Scan Test Software ( Optional )

1. Boundary Scan uses simple 5-wire connector (J-TAG) to interface to the PCB under test, eliminating the need for test pin contact (Virtual Test Pin Test Concept).
2. Using Boundary Scan Software package and vendor supplied BSD Files, tests such as ID Code Read, User Code Read, BS Length, Chain Test, Integrity Test and Open / Short can be performed.
3. Learn and compare for open / short test, where no netlist is available.

Advanced Boundary Scan Test Software (Optional)

1. Provides interactive mode to set logic levels at various pins and read back.
2. Functional Test for BS devices and Non Boundary Scan Devices (Glue Logic Chips.).
3. With Card Edge connector wired to v200 test channels and with JTAG PCB Track integrity and static functional tests can be carried out.