TestDirector6

TestDirector6 is Qmax’s Suite of Test Software for its newest generation of testers. It offers powerful and user-friendly tools to complement the proven hardware from Qmax products supporting PCB Test. Its modular design with graphical user interface allows the user to quickly develop and debug test applications.

TD6 utilizes multiple Software modules to support the test and repair of Electronic Assemblies / Subsystems and Devices. Each element of TD6 is a generic test tool that can be easily tailored / configured for a specific test application. Details..

Description:

TestDirector6 is Qmax’s Suite of Test Software for its newest generation of testers. It offers powerful and user-friendly tools to complement the proven hardware from Qmax products supporting PCB Test. Its modular design with graphical user interface allows the user to quickly develop and debug test applications.

TD6 utilizes multiple Software modules to support the test and repair of Electronic Assemblies / Subsystems and Devices. Each element of TD6 is a generic test tool that can be easily tailored / configured for a specific test application. TD6 is designed to allow easy integration of additional capabilities / options to support future application requirements.

TD6 will run on Windows XP / Vista and Windows 7 Operating Systems.

The Main Elements of TD6 include:

Interactive workstation, Test Sequencer, Test station and Integrated Device Development Environment.

  • Interactive WorkStation is for instant test of devices on a board without creating TPS (Test Program Set) for a Circuit board or Unit under Test (i.e. UUT). Use of TD6 Interactive WorkStation requires the Test hardware connected to the host computer in order to operate (On-Line only)

  • Test Sequencer supports development of TPS for a Board or UUT. Test Sequencer can be used Off-Line allowing Test Program development to be accomplished without tying the test resources. TD6 allows Off-Line simulation for validating the test vector adequacy and includes fault coverage report before testing it in the actual ATE system.

  • Test Station provides structured execution of Test Programs Set (TPS) with automated logging of results. Test Station does not allow modification of Test sequencer tolerance limits. Test Station requires tester hardware to be connected to the host computer (On-Line only)

  • IDTE is primarily used for developing Device Level Test Programs and added to user libraries for use in TD6 Interactive, TestSequencer or TestStation. TD6 IDTE is designed to suit the needs of testing all category of devices/IC's. For Functional Description of devices in Gate Level QDDL can be used. For Functional or Behavioural Description VHDL can be used. For defining the expected values or using expressions for digital, analog or mixed signal PythonTD can be used.. Depending upon the type of device and its complexity we may choose one of the above methods of programming the device test program.

Features of TD6 :

  • Allows application of multiple test methodologies to support testing and repair of modern and legacy circuit boards.
  • Automated process supports repair of high volume boards with minimal time.
  • Supports test and repair of undocumented boards.
  • Ability to identify unknown or house coded devices.
  • Uses IEEE standard VHDL simulator with minimal manual inference for Digital Devices.
  • Optional Spice simulator and PythonTD, high level language text editor for generation of test programs for analog and Mixed Signal Devices
  • Testing of latest generation boards with high density/ high pin count devices using boundary scan test.
  • Learn and compare facility for non-simulator based board programs.
  • Board program with Guided probe backtracking algorithms for diagnostics and troubleshooting.
  • Fault Simulation and Fault Dictionary (Optional) for board test.
  • Support for up to 8 Event Frame definition with different basic timing units (BUT) and Duration.
  • Support for Event Pulse definition for data formatting capability (Edge placement) and Measurement timings.
  • Conditional and Unconditional Loops for up to 32k iterations for board or UUT initialization and Clock generation without consuming Pin Memory space.
  • Functional testing of Devices in In-circuit mode with automatic guarding Guide and out circuit mode for testing loose devices.
  • Advanced QSMVI learn and compare with auto BEST curve fit
  • IEEE 1149 complaint JTAG port boundary scan test with synchronous digital IO channels
  • In-built Precision Measurement Units (PMU) to test DC parameters such as input Bias currents, Fan-out capability and tri-state leakage of devices on board.
  • Measurement of AC parametric values such as pulse width, propagation delay, rise and fall time of output signals in nano second accuracy.
  • BUS cycle Signature Test (Qmax Patented) for CPU based Boards using Learn and Compare technique.
  • PXI Instrumentation and Analog switch matrix.
  • Test Station for operator level software along with Statistical Data and failure analysis.
  • Optional TestDirector6 Integrated Device Test Environment (IDTE) for development of new device models.
  • Optional Circuit-Tracing feature for Reverse Engineering applications. Schematic generation capability with optional CAD package or net-list export facility.

Optional Add-ons Of TD6:

External Instrumentation Tests for IEEE or PXI

The PXI instruments are connected to the ATE application through Analog Highways. In order to use the PXI Instruments, the required analog highway cards must be installed. The Analog Highway interfaces the PXI instrumentation to appropriate test platform test pins under software control. The Highway channels are bi-directional paths of force or sense signals. Signals up to 30 MHz can be switched through this highway. Analog highways can handle maximum DC voltage of +/-100V with current carrying capacity up to 0.5A.

Fault Simulation (Optional)

While using QDDL or VHDL Simulator, Fault Simulator automatically inserts stuck-at-zero (0), stuck-at-one (1) and open (Z) faults in every node in a board and checks that the test program is capable of detecting them. If the test program covers all the simulated faults, then the confidence is stated as 100%. This helps the ATE Manager to evaluate the test programs before they are put in use. In Learn and Compare technique, insertion of faults and their detection has to be performed manually.

Fault Dictionary (Optional)

Though one can troubleshoot a Board using Functional Test and Guided Probe back tracking, the result depends on accuracy of the operator in placing the probe on the right nodes. Operator error may lead to incorrect diagnosis. Also in High density Boards it may be difficult to probe certain nodes and conformal coating may make it more difficult. At times it may not be possible to probe parts of a board when there are daughter boards on top of the main board. Fault Dictionary provides a mean to improve diagnosis under these circumstances. By the use of Fault Simulation Software, all possible faults are considered and the resulting output CRC is learnt virtually. By looking at the CRC code of failure, the system software is able to suggest probable failing components without having to probe all or if not none. Thus Fault Dictionary greatly minimizes manual probing.

Reverse Engineering (Optional)

Circuit Tracer

All the available Digital channels (Upto 320/640) can be used for Reverse engineering (Circuit-Tracing and Schematic Generation applications) by using the Qmax Circuit Tracing software and when it is used along with EDWIN software package, the user can reverse engineer the PCB by creating the schematic diagrams of the PCBs for which there are no circuit diagrams.

User can define any number of Clips / probes and the system will generate the sequence of placing the clips and probes automatically. The links between devices pins can be learnt and a net list generated. The resistance threshold for a link can be defined by the user.

New Updates on TD6 :

Qmax TestDirector6 (TD6) software, which runs under Windows XP / Windows Vista / Windows 7, consists of TD6 Interactive WorkStation for instant test of a PCB using Qmax's General Purpose Test adapter, TD6 TestSequencer (TPS Development Studio) for sequencing various tests for a board functional test and TD6 TestStation for operator level use of the Test Program Set (TPS). Optional Software packages are TD6 Integrated Device Test Environment (IDTE) for developing new device test programs and TD6 CircuitTracer (CT) for reverse engineering application of un documented PCBs.

TD6 TestStand (Optional)

The TD6 TestStand will enable the users to sequence and execute their own test programs. The user can browse his/her test program and add to it the TD6 TestStand component. The test program can either be in the form of DLL ( Dynamic Link Library ) or in the form of EXE ( Executable ). The user can add 'n' number of steps. Qmax TestStand will support the .Net based test programs. Each and every individual assembly or exe added in the TestStand component will be considered as a single step. All such steps on the whole added in the TestStand component will be considered as 'Sequence'.



Spice Simulation (Optional)

SPICE (Simulation Program with Integrated Circuit Emphasis) is an analog electronic circuit simulator used in board-level design to check the integrity of circuit designs and to predict circuit behavior. SPICE model for analog and mixed signal devices will be available in Qmax Library for use in Out-Circuit, Board Functional Test using edge connector. The software suits for more complex industry requirements with the support for Diodes, Transistors, Op-amps, Comparators, Opto couplers, Regulators, A/D & D/A converters. Spice models will be supported for 8000+ Analog/Mixed devices. Component level spice simulation can be done in offline as well as in online mode.

Automatic Test Pattern Generator (ATPG) (Optional)

ATPG is an electronic design automation method used to find an input test sequence that, when applied to a digital circuit, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. The generated patterns are used to test semiconductor devices on board after manufacture, and used to assist with determining the cause of failures.

Automatic Test Pattern generation helps the user to test Digital - Board / Device Functional Test using edge connectors., This will save considerable time in TPS development as 80% of the time taken for developing a TPS in constructing test vector and especially for complex digital circuits using state machines, registers and memory based devices.